1. Field of the Invention
The present invention relates in general to the manufacturing and testing of integrated circuits, and it more particularly relates to a method for locating one or more individual integrated circuits, or dies, on a wafer containing a plurality of dies.
2. Background Information
Integrated circuits of the general type with which the present invention is concerned, are produced by passing a wafer through several consecutive manufacturing and testing stages. The wafer is typically substantially circular in shape, and is usually between two to six inches in diameter. The manufacturing stage includes a construction stage during which the integrated circuits, or dies are formed on the wafer, while the testing stage includes identifying and isolating the defective dies. A separation stage and a packaging stage yield the operative dies, in preparation for shipment and installation.
A wafer is typically capable of holding several hundreds of individual dies. Of these dies, only a relatively small percentage, often between ten percent (10%) to over fifty percent (50%) percent are operative, while the remaining dies are defective, and therefore unusable. The reasons for such a low yield usually relate to extremely high precision requirements of the manufacturing process, as well as the level of existing impurities.
While various attempts have been suggested to improve the yield of the testing process, none has proven to be entirely satisfactory. One such attempt is described in U.S. Pat. No. 4,607,525 to Turner et al., which relates to a height measuring device. The patented device is a profiling and testing system which utilizes an air probe to determine the contour of a wafer, in order to enable an electrical sensor to step from die to die, and to test the completed dies in the water.
The patented device utilizes a pressure transducer for determining the locations of the physical edge of the wafer. Lines are then traced between these edges for geometrically determining the center of the wafer, and defective dies are then located relative to the center. While the patented device may have been successful in simplifying the tracing of the wafer profile, it has not improved substantially the overall yield of the manufacturing process.
The relative inefficiency of the patented device can be exemplified by the use of edge sensors, for locating the reference edges or unique features or dies on the wafer. As it is well known in the art, an edge sensor may cause substantial damage to the sensitivity constructed dies on the wafer, such as by weakening, or even breaking the conductive rings which generally surround the electronic circuits of the dies. As a result, it is not uncommon for some dies to be tested as functional, and to become defective after packaging, or shortly after installation.
The replacement of circuit boards having such inherently defective, but apparently operative dies installed thereon, is relatively expensive, and particularly inefficient, for reasons that are obvious to those skilled in the art. Furthermore, an edge sensor can become defective, due to the recurring impact with the edges of the wafer, and it can require periodic replacement or maintenance. Such maintenance can cause the manufacturing process to be continuously hampered, interrupted and delayed.
Thus, there is a need for a new and improved method for profiling wafers, and for locating accurately and identifying uniquely the complete or unique dies manufactured thereon. The method should improve the yield of the conventional manufacture and testing of the micro-electronic circuits, and it should further dispense with the use of edge sensors for profiling the wafer, and with the requirement for unique reference points that do not substantially contribute to the improvement of the yield.
The electrical testing stage of the wafer is essential for the overall manufacturing process, since the testing must detect and identify the functional dies to be packaged, as well as the defective dies which should be discarded. In order for the conventional electrical testing to work properly, the connection points, or pads, of the dies must be aligned accurately with the probes of the tester. In this regard, even a relatively minute misalignment of the dies may cause the functional dies to be incorrectly identified as defective, and thus to be wastefully discarded.
Automatic wafer probers are typically used to move the dies underneath the probes of the testing in a very precise manner to minimize the risk of misalignment. After the testing stage is completed, the functional dies must be identified and separated from the defective dies, so that only the operative dies are subsequently packaged for shipment or installation.
Conventionally, the defective dies are visually identified by inking or scratching. The identification process may be done either "on-line" or "off-line". When the dies are identified "on-line", the defective dies are usually scratched or inked immediately after the test is completed. When the dies are identified "off-line", the defective dies are scratched or inked after all the dies have been tested as a separate process step.
Several problems are associated with the foregoing conventional identification process. For example, the scratching of the dies can cause them to become irreversibly altered. In some instances, the probes of the tester may be misaligned, the entire wafer may be incorrectly marked, and the dies may be inaccurately identified as defective. As a result, the entire wafer is rejected, and the manufacturing cost is substantially increased, and rendered prohibitively expensive.
While the alternative inking process is partially reversible, it is common for the ink to come in contact with the pads of adjacent operative dies, rendering them defective and unusable. Furthermore, the ink is generally at the base of epoxy, and cannot be easily removed, particularly after it has been exposed to relatively high temperatures. Therefore, it is preferable to wait until all the dies on the wafer have been tested, prior to commencing the marking process.
Thus, there is a need for a new and improved profiling process, which, in addition to enabling the accurate identification of the dies on the wafer, and in addition to improving the yield of the conventional manufacture of the microelectronic circuits, dispenses with the use of the foregoing harmful conventional visual marking techniques.
Conventionally, the "off-line" identification of the dies requires that a substantially exact alignment be maintained between the wafer on the wafer prober in the tester, and the wafer on the prober in the inker. A relatively minute misalignment can result in an incorrect marking of the dies, and can thus contribute to a substantial decrease in the production yield.
Therefore, there is a need for a new and improved process which increases the alignment tolerance of the manufacture process, and which accommodates physical shifts of the wafer.
Another concern associated with the conventional profiling methods, has been the exclusion of the dies within a peripheral zone by an automatic wafer stepper. Such zonal dies are generally undesirable, since they can be structurally incomplete, such as by missing a corner or a portion of a side. Thus, while the testing of such zonal dies may indicate their proper functionality, such dies need to be rejected, in order to prevent potential costly remedial steps after installation. An additional concern associated with the zonal or peripheral dies has been the damage caused to the probe card during the testing stage.
Therefore, it is highly desirable to have a new and improved method for profiling wafers, and for locating accurately and identifying uniquely the dies manufactured thereon. The method should improve the yield of the conventional manufacture of the micro-electronic circuits, and it should further dispense with the use of the edge sensors, for profiling the wafer, or for accurately locating dies thereon.
The new and improved profiling process, should dispense with the use of the conventional visual inking and scratching marking techniques, and it should exclude the peripheral dies, which are physically or electronically whole, without causing damage to the testing probe. The inventive method should further be compatible with automatic wafer probers from different manufacturers.